(1) Field of the Invention:
The present invention relates to a semiconductor device, and more particularly to a semiconductor device which comprises a high voltage withstanding vertical MOS transistor and a low voltage withstanding element, both formed on the same chip.
(2) Description of the Prior Art:
FIG. 1 is a sectional view of a known vertical MOS field effect transistor (hereinafter called "MOSFET"). The MOSFET comprises an n.sup.+ -type silicon substrate 1. On the silicon substrate 1 an n-type epitaxial silicon layer 2 is formed. In the layer 2, p-type impurity regions 3, 3' are formed, both having a surface flush with the surface of the layer 2. Further, n.sup.+ -type impurity regions 4, 4' are formed in the p-type impurity regions 3, 3', respectively. The n.sup.+ -type impurity regions 4 and 4' have surfaces flush with those of the p-type impurity regions 3 and 3', respectively. These regions 3, 3', 4 and 4' are formed by double diffusion method.
On the entire upper surface of the n-type layer 2 there is formed an oxide film 6. The film 6 has thin portions 5 and 5'. The thin portion 5 lies partly on that portion of the region 3 which faces the region 3' and partly on that portion of the region 4 which is continuous to said portion of the region 3. Similarly, the thin portion 5' lies partly on that portion of the region 3' which faces the region 3 and partly on that portion of the region 4' which is continuous to said portion of the region 3'. The oxide film 6 has two contact holes at such positions that the p-type impurity region 3 and the n.sup.+ -type impurity region 4 are partly exposed through one of the holes and the p-type impurity region 3' and the n.sup.+ -type impurity region 4' are partly exposed through the other hole. A gate electrode 7 is formed on the thin portions 5 and 5' of the oxide film 6 and on that portion of the film 6 which lies between the thin portions 5, 5'. Further, a source electrode 8 is provided which is in ohmic contact with the p-type impurity region 3 and the n.sup.+ -type impurity region 4 through one of said contact holes. Another source electrode 8' is provided which is also in ohmic contact with the p-type impurity region 3' and the n.sup.+ -type impurity region 4' through the other contact hole. A drain electrode 9 is formed on the lower surface of the n.sup.+ -type silicon substrate 1.
When the vertical MOSFET of FIG. 1 is operated, a channel inversion layer is formed in that portion of either p-type impurity region which lies below the gate electrode 7. Then, the n.sup.+ -type impurity regions 4, 4' function as a source, whereas the n-type epitaxial silicon layer 2 functions as a drain. As a result, drain current flows in the direction of arrows as shown in FIG. 1. At the same time, the voltage applied between the source and the drain generates in the n-type epitaxial layer 2 such an electric field having such intensity distribution as shown by broken lines.
The vertical MOSFET has no minority carrier storage effect. It has therefore high-speed switching characteristic and good high-frequency characteristic. In addition, for its positive thermal coefficient of resistivity it scarcely undergoes secondary breakdown. Because of these desirable electrical properties the vertical MOSFET is used as a high voltage withstanding, large output element. In particular, it is useful as an element to deliver a large output from a circuit including bipolar transistors. (Hereinafter, a circuit including bipolar transistors and vertical MOSFETs will be called "BiMOS circuit".)
FIG. 2 is a circuit diagram of a BiMOS circuit. The BiMOS circuit is a converter circuit for a three-phase induction motor, which has a vertical MOSFET provided at the output stage. Semiconductor devices similar to such BiMOS circuit as shown in FIG. 2, i.e. integrated circuits including vertical MOSFETs and low voltage withstanding elements such as bipolar transistors--all formed on a single chip, are now increasingly demanded. If low voltage withstanding elements such as bipolar transistors are to be formed in the epitaxial layer 2 of such a vertical MOSFET as shown in FIG. 1, the following problems arise.
First, in the vertical MOSFET shown in FIG. 1 the n-type epitaxial layer 2 must be made so thick that a depletion layer may extend far enough to provide a sufficiently high withstand voltage between the source and drain. If a low voltage withstanding element is formed in the n-type epitaxial layer 2, it is necessary to make the layer 2 thinner in order to reduce the series resistance of the element. Hence, if a circuit such as BiMOS circuit which comprises a vertical MOSFET and a circuit including a low voltage withstanding element is to be formed on a single semiconductor substrate, either the withstand voltage of the vertical MOSFET or the series resistance of the adjacent circuit should inevitably be sacrificed. In other words, both the withstand voltage and the series resistance cannot be improved to a satisfactory degree. Further, if the epitaxial layer 2 is made thick, thus ensuring the high voltage withstand characteristic of the vertical MOSFET, another problem will arise in addition to the rising of the series resistance of the adjacent circuit. That is, as evident from the drain current flow shown in FIG. 1, on-resistance of the vertical MOSFET will unavoidably increase.